A phase detector circuit generates an output signal that is indicative of the phase difference between two periodic input signals. A zero phase detector ideally generates a zero output when the two periodic input signals are aligned in phase with each other. Zero phase detectors are used in many applications including delay-locked loops (DLLs). As data rates increase in modern data transmission systems, the DLLs in high-speed data transmission systems require faster zero phase detectors. However, conventional zero phase detectors have a modest speed limit before generating a hard failure.
High-speed zero phase detectors have complex circuit architectures that consume a large amount of power and die area. An XOR based quadrature phase detector can operate at a relatively high speed, but it generates a zero output signal when the periodic input signals are 90 degrees out of phase. Therefore, it would be desirable to provide a similarly high-speed zero phase detector that generates a zero output signal when the periodic input signals are in phase and that does not have many of the problems of conventional zero phase detectors.
It would also be desirable to provide a high-speed delay-locked loop (DLL) that converges to the point at which the periodic input signals of the phase detector are aligned in phase. In one type of DLL, the frequency of a high-speed reference clock signal is divided by an input frequency divider circuit to generate a lower speed clock signal. The lower speed clock signal is provided to the input of a low speed phase detector in the DLL. The input frequency divider circuit consumes a significant amount of power and generates a substantial amount of jitter in the output clock signal. Therefore, it would be desirable to provide a high-speed DLL that consumes less power and generates less jitter in the output clock signal.